import StmtFSM::*;
import Uart::*;

(* synthesize *)
module mkTb();
      Uart_ifc uart <- mkUart();

      Stmt s = seq
            delay(8);
            uart.load(8'h55);
            uart.load(8'haa);
            uart.load(8'hc3);
            uart.load(8'h3c);
            await(uart.done());
            $finish;
      endseq;
      
      mkAutoFSM(s);

endmodule
 

$ bsc -u -sim Tb.bsv; bsc -sim -e mkTb -o Tb.exec; ./Tb.exec -V bsim.vcd; gtkwave -A bsim.vcd

`timescale 1ns/1ns
module top();
      /*AUTOREGINPUT*/
      // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
      reg      CLK;        // To mkTb_inst of mkTb.v
      reg      RST_N;        // To mkTb_inst of mkTb.v
      // End of automatics
      /*AUTOWIRE*/
      mkTb mkTb_inst(/*AUTOINST*/
      // Inputs
      .CLK    (CLK),
      .RST_N    (RST_N));

      initial begin
            RST_N = 1'b0;
            #10;
            RST_N = 1'b1;
      end
      initial begin
            CLK = 1'b0;
            forever begin
        #5 CLK = ~CLK;
            end
      end
      initial begin
            $dumpfile("verilog.vcd");
            $dumpvars;
      end
endmodule // top

$ bsc -u -verilog Tb.bsv; iverilog top.v mkTb.v mkUart.v -o ./mkTb.exev; ./mkTb.exev; gtkwave -A verilog.gtkw