interface Fib_ifc;
   method int read();
endinterface

(* synthesize, always_ready, always_enabled *)
module mkFibOne(Fib_ifc);
   Reg#(int) this_fib <- mkReg(0);
   Reg#(int) next_fib <- mkReg(1);

   rule fib;
      this_fib <= next_fib;
      next_fib <= this_fib + next_fib;  // note that this uses stale this_fib
   endrule: fib

   method int read();
      return this_fib;
   endmethod

endmodule: mkFibOne

       Reg#(int) this_fib <- mkReg(0);

    Interface_type identifier <- module_name;

$ bsc -verilog FibOne.bsv
Verilog file created: mkFibOne.v

//
// Generated by Bluespec Compiler (build 38534dc)
//
// On Wed Mar 25 09:12:14 JST 2020
//
//
// Ports:
// Name                         I/O  size props
// read                           O    32 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkFibOne(CLK,
        RST_N,

        read);
  input  CLK;
  input  RST_N;

  // value method read
  output [31 : 0] read;

  // signals for module outputs
  wire [31 : 0] read;

  // register next_fib
  reg [31 : 0] next_fib;
  wire [31 : 0] next_fib$D_IN;
  wire next_fib$EN;

  // register this_fib
  reg [31 : 0] this_fib;
  wire [31 : 0] this_fib$D_IN;
  wire this_fib$EN;

  // value method read
  assign read = this_fib ;

  // register next_fib
  assign next_fib$D_IN = this_fib + next_fib ;
  assign next_fib$EN = 1'd1 ;

  // register this_fib
  assign this_fib$D_IN = next_fib ;
  assign this_fib$EN = 1'd1 ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        next_fib <= `BSV_ASSIGNMENT_DELAY 32'd1;
    this_fib <= `BSV_ASSIGNMENT_DELAY 32'd0;
      end
    else
      begin
        if (next_fib$EN) next_fib <= `BSV_ASSIGNMENT_DELAY next_fib$D_IN;
    if (this_fib$EN) this_fib <= `BSV_ASSIGNMENT_DELAY this_fib$D_IN;
      end
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    next_fib = 32'hAAAAAAAA;
    this_fib = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkFibOne

`timescale 1ns/1ps
 
module tb_mkFibOne;
   /*AUTOREGINPUT*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg          CLK;            // To mkFibOne of mkFibOne.v
   reg          RST_N;          // To mkFibOne of mkFibOne.v
   // End of automatics
   /*AUTOWIRE*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [31:0]      read;           // From mkFibOne of mkFibOne.v
   // End of automatics
   mkFibOne mkFibOne (/*AUTOINST*/
              // Outputs
              .read     (read[31:0]),
              // Inputs
              .CLK      (CLK),
              .RST_N        (RST_N));
   
   initial begin
      RST_N = 1'b0;
      #30;
      RST_N = 1'b1;
      forever begin
       if (CLK) $display("%0d", read);
       if (read > 10000) $finish;
       #10;
      end
   end
   
   initial begin
      CLK = 1'b0;
      forever begin
     #5 CLK = ~CLK;
      end
   end
   
   initial begin
      $dumpfile("tbmkFibOne.vcd");
      $dumpvars(0,mkFibOne);
   end
   
endmodule 

$ iverilog tbmkFibOne.v mkFibOne.v -o mkFibOne.exev
$ ./mkFibOne.exev
VCD info: dumpfile tbmkFibOne.vcd opened for output.
         0
         1
         1
         2
         3
         5
         8
        13
        21
        34
        55
        89
       144
       233
       377
       610
       987
      1597
      2584
      4181
      6765
     10946

(* synthesize *)
module mkFibOne();
   // register containing the current Fibonacci value
   Reg#(int) this_fib();              // interface instantiation
   mkReg#(0) this_fib_inst(this_fib); // module instantiation
   // register containing the next Fibonacci value
   Reg#(int) next_fib();
   mkReg#(1) next_fib_inst(next_fib);

   rule fib;  // predicate condition always true, so omitted
      this_fib <= next_fib;
      next_fib <= this_fib + next_fib;  // note that this uses stale this_fib
      $display("%0d", this_fib);
      if ( this_fib > 10000 ) $finish(0) ;
  endrule: fib
endmodule: mkFibOne

   // register containing the current Fibonacci value
   Reg#(int) this_fib();              // interface instantiation
   mkReg#(0) this_fib_inst(this_fib); // module instantiation
   // register containing the next Fibonacci value
   Reg#(int) next_fib();
   mkReg#(1) next_fib_inst(next_fib);

      this_fib <= next_fib;
      next_fib <= this_fib + next_fib;  // note that this uses stale this_fib

$ bsc -sim  FibOne.bsv
Elaborated module file created: mkFibOne.ba
$ bsc -sim -e mkFibOne -o mkFibOne.exec
Bluesim object created: mkFibOne.{h,o}
Bluesim object created: model_mkFibOne.{h,o}
Simulation shared library created: mkFibOne.exec.so
Simulation executable created: mkFibOne.exec

$ ./mkFibOne.exec
0
1
1
2
3
5
8
13
21
34
55
89
144
233
377
610
987
1597
2584
4181
6765
10946

$  bsc -verilog FibOne.bsv
Verilog file created: mkFibOne.v

//
// Generated by Bluespec Compiler (build 38534dc)
//
// On Mon Mar 23 06:33:47 JST 2020
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
   `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
   `define BSV_RESET_VALUE 1'b1
   `define BSV_RESET_EDGE posedge
`else
   `define BSV_RESET_VALUE 1'b0
   `define BSV_RESET_EDGE negedge
`endif

module mkFibOne(CLK,
                RST_N);
   input  CLK;
   input  RST_N;

   // register next_fib_inst
   reg [31 : 0] next_fib_inst;
   wire [31 : 0] next_fib_inst$D_IN;
   wire next_fib_inst$EN;

   // register this_fib_inst
   reg [31 : 0] this_fib_inst;
   wire [31 : 0] this_fib_inst$D_IN;
   wire this_fib_inst$EN;

   // register next_fib_inst
   assign next_fib_inst$D_IN = this_fib_inst + next_fib_inst ;
   assign next_fib_inst$EN = 1'd1 ;

   // register this_fib_inst
   assign this_fib_inst$D_IN = next_fib_inst ;
   assign this_fib_inst$EN = 1'd1 ;

   // handling of inlined registers

   always@(posedge CLK)
      begin
         if (RST_N == `BSV_RESET_VALUE)
            begin
               next_fib_inst <= `BSV_ASSIGNMENT_DELAY 32'd1;
               this_fib_inst <= `BSV_ASSIGNMENT_DELAY 32'd0;
            end
         else
            begin
               if (next_fib_inst$EN)
                  next_fib_inst <= `BSV_ASSIGNMENT_DELAY next_fib_inst$D_IN;
               if (this_fib_inst$EN)
                  this_fib_inst <= `BSV_ASSIGNMENT_DELAY this_fib_inst$D_IN;
            end
      end

   // synopsys translate_off
   `ifdef BSV_NO_INITIAL_BLOCKS
   `else // not BSV_NO_INITIAL_BLOCKS
   initial
   begin
      next_fib_inst = 32'hAAAAAAAA;
      this_fib_inst = 32'hAAAAAAAA;
   end
   `endif // BSV_NO_INITIAL_BLOCKS
   // synopsys translate_on

   // handling of system tasks

   // synopsys translate_off
   always@(negedge CLK)
   begin
      #0;
      if (RST_N != `BSV_RESET_VALUE) $display("%0d", $signed(this_fib_inst));
      if (RST_N != `BSV_RESET_VALUE)
      if ((this_fib_inst ^ 32'h80000000) > 32'h80002710) $finish(32'd0);
   end
   // synopsys translate_on
endmodule  // mkFibOne

`timescale 1ns/1ps
 
module tb_mkFibOne;
   /*AUTOREGINPUT*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg          CLK;            // To mkFibOne of mkFibOne.v
   reg          RST_N;          // To mkFibOne of mkFibOne.v
   // End of automatics
   /*AUTOWIRE*/
   mkFibOne mkFibOne (/*AUTOINST*/
              // Inputs
              .CLK      (CLK),
              .RST_N        (RST_N));
   
   initial begin
      RST_N = 1'b0;
      #30;
      RST_N = 1'b1;
   end
   
   initial begin
      CLK = 1'b0;
      forever begin
     #5;
     CLK = ~CLK;
      end
   end
   
   initial begin
      $dumpfile("tbmkFibOne.vcd");
      $dumpvars(0,mkFibOne);
   end
   
endmodule 

$ iverilog tbmkFibOne.v mkFibOne.v -o mkFibOne.exev
$ ./mkFibOne.exev 
VCD info: dumpfile tbmkFibOne.vcd opened for output.
0
1
1
2
3
5
8
13
21
34
55
89
144
233
377
610
987
1597
2584
4181
6765
10946

$ gtkwave -f tbmkFibOne.vcd
GTKWave Analyzer v3.3.111 (w)1999-2020 BSI

[0] start time.
[520000] end time.

    always @ (posedge CLK) begin
        if (cond2)
            y <= y - 1;
        else if (cond1) begin
            y <= y + 1;
            x <= x - 1;
        end else if (cond0)
            x <= x + 1;
    end

        if (cond2)
            y <= y - 1;
        else if (cond1) begin
            y <= y + 1;

        if (cond1) begin
            x <= x - 1;
        end else if (cond0)
            x <= x + 1;

    cond2

    !cond2 && cond1

    !(!cond2 && cond1) && cond0

        if (cond2)
            y <= y - 1;

        if (!cond2 && cond1) begin
            y <= y + 1;
            x <= x - 1;
        end 

        if (!(!cond2 && cond1) && cond0))
            x <= x + 1;

    rule proc0 (cond0);
        x <= x + 1;
    endrule

    rule proc1 (cond1);
        y <= y + 1;
        x <= x - 1;
    endrule

    rule proc2 (cond2);
        y <= y - 1;
    endrule
    (* descending_urgency = “proc2, proc1, proc0” *)

    assign x$EN = WILL_FIRE_RL_proc0 || WILL_FIRE_RL_proc1 ;
    assign y$EN = WILL_FIRE_RL_proc1 || cond2 ;

    assign WILL_FIRE_RL_proc0 = cond0 && !WILL_FIRE_RL_proc1 ;
    assign WILL_FIRE_RL_proc1 = cond1 && !cond2 ;

    (cond0 && !(cond1 && !cond2)) || (cond1 && !cond2)

    (cond1 && !cond2) || cond2

reg [31:0] burst_count, dest_burst_size ;
reg        burst_in_progress ;
...
always @(posedge clk)    // burst_in_progress_stop 
begin
   if (burst_in_progress && (burst_count==dest_burst_size))
       burst_in_progress <= False;
   ...
end 

always @(posedge clk)    // burst_count;
begin  
   burst_count <= burst_in_progress ? burst_count+1 : 0;
   ...
end

Reg#(Data_t) dest_burst_size <- mkReg (32'h0) ;
Reg#(Data_t) burst_count     <- mkReg (0) ;
Reg#(Bool) burst_in_progress  <-  mkReg (False) ;

rule burst_in_progress_stop (burst_in_progress && (burst_count==dest_burst_size));
   burst_in_progress <= False;
   ...
endrule

rule burst_counting ;
   burst_count <= burst_in_progress ? burst_count + 1 : 0;
   ...
endrule

Reg#(Data_t) dest_burst_size <- mkReg (32'h0) ;
Reg#(Data_t) burst_count     <- mkReg (0) ;
Reg#(Bool) burst_in_progress  <- mkReg (False) ;

rule burst_in_progress_stop (burst_in_progress) ;
   burst_in_progress <= burst_count != dest_burst_size ;
   burst_count <= (burst_count != dest_burst_size)  ? burst_count+1 : 0;      
   ...
endrule