Article #387

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posted by sakurai on April 22, 2021 #387

ソースファイル

以下にサンプルのステートマシンのソースを示します。

testFSM.bsv

import StmtFSM::*;
interface FSM_ifc;
   method State read();
endinterface

typedef enum { IDLE, STEP1, STEP2, STEP3, STOP } State deriving(Bits,Eq);

(* synthesize, always_ready, always_enabled *)
module testFSM(FSM_ifc);
   Reg#(State) state <- mkReg(IDLE);
   Reg#(int) counter <- mkReg(0);

   rule runCounter;
      if (counter == 100) begin
         \$display("Done");
         \$finish;
      end
      counter <= counter + 1;
   endrule

   rule stateIdle ( state == IDLE ); //default state
      \$display("Counter = %3d, State: IDLE", counter);
      if (counter % 4 == 0)
         state <= STEP1;
   endrule

   rule stateStep1 ( state == STEP1 );
      \$display("Counter = %3d, State: STEP1", counter);
      if (counter % 8 == 0)
         state <= STEP2;
   endrule

   rule stateStep2 ( state == STEP2 );
      \$display("Counter = %3d, State: STEP2", counter);
      state <= STOP;
   endrule

   rule stateSTOP ( state == STOP );
      \$display("Counter = %3d, State: STOP", counter);
      state <= IDLE;
   endrule

   method State read();
      return state;
   endmethod
endmodule: testFSM

これをドライブする上位モジュールの原始ファイルを以下に示します。

top.v

`timescale 1ns/1ns

module top();
   /*AUTOREGINPUT*/
   /*AUTOWIRE*/
   testFSM testFSM_inst(/*AUTOINST*/);

   initial begin
      RST_N = 1'b0;
      #10;
      RST_N = 1'b1;
   end

   initial begin
      CLK = 1'b0;
      forever begin
         #5 CLK = ~CLK;
      end
   end

   initial begin
      \$dumpfile("testFSM.vcd");
      \$dumpvars;
   end
endmodule


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