次にMakefileを示します。

# BSV simulation Makefile (done版 / drain版 併存)
#   done版  : Tb.bsv + Uart.bsv           → run / wave / vrun / vwave
#   drain版 : TbDrain.bsv + UartDrain.bsv → drain-run / drain-wave / drain-vrun / drain-vwave
#   make clean : 生成物の削除

.PHONY: all run wave vrun vwave drain-run drain-wave drain-vrun drain-vwave clean

all: run

# ==== done版 ====

# ---- Bluesim ----
Tb.exec: Tb.bsv Uart.bsv
	bsc -u -sim Tb.bsv
	bsc -sim -e mkTb -o Tb.exec

bsim.vcd: Tb.exec
	./Tb.exec -V bsim.vcd

run: bsim.vcd

wave: bsim.vcd
	gtkwave -A bsim.vcd &

# ---- Verilog sim ----
mkTb.exev: Tb.bsv Uart.bsv
	bsc -u -verilog Tb.bsv
	bsc -verilog -e mkTb -o mkTb.exev

verilog.vcd: mkTb.exev
	./mkTb.exev +bscvcd=verilog.vcd

vrun: verilog.vcd

vwave: verilog.vcd
	gtkwave -A verilog.vcd &

# ==== drain版 ====

# ---- Bluesim ----
TbDrain.exec: TbDrain.bsv UartDrain.bsv
	bsc -u -sim TbDrain.bsv
	bsc -sim -e mkTbDrain -o TbDrain.exec

bsim_drain.vcd: TbDrain.exec
	./TbDrain.exec -V bsim_drain.vcd

drain-run: bsim_drain.vcd

drain-wave: bsim_drain.vcd
	gtkwave -A bsim_drain.vcd &

# ---- Verilog sim ----
mkTbDrain.exev: TbDrain.bsv UartDrain.bsv
	bsc -u -verilog TbDrain.bsv
	bsc -verilog -e mkTbDrain -o mkTbDrain.exev

verilog_drain.vcd: mkTbDrain.exev
	./mkTbDrain.exev +bscvcd=verilog_drain.vcd

drain-vrun: verilog_drain.vcd

drain-vwave: verilog_drain.vcd
	gtkwave -A verilog_drain.vcd &

clean:
	rm -f *.bo *.ba *.cxx *.h *.o *.so *.exec *.exev mk*.v *.vcd *~

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